Instruments and Systems: Monitoring, Control, and Diagnostics Annotation << Back Method of Correction and Detection of Errors in Information Storage and Transmission Devices A.A. PAVLOV, A.N. TSARKOV, YU.A. ROMANENKO, A.YU. ROMANENKO, M.I. MIHEEV, F.A. PAVLOV A regular procedure for coding information for correcting single errors and detecting double errors is described while reducing information redundancy by one check bit and, therefore, hardware costs associated with storing check bit values in a memory device. Regularities are revealed that allow, during decoding, to form additional checks of the error sign to determine the erroneous digits in the event of indistinguishable error syndromes. A comparative assessment of the detecting ability and information redundancy of the proposed method with a modified Hamming code is carried out on the example of encoding an 11-bit information word. The proposed code allows you to correct all single errors, detect all double errors and, at the same time, correct 27 % of double errors. Reducing information redundancy allows you to increase the code rate and reduce hardware costs associated with storing the values of a given bit in the memory and, therefore, increase the likelihood of failure-free operation and the reliability of the memory device while reducing information and hardware redundancy. Keywords: correcting linear code, information bits, check bits, error syndrome, single and double errors, information redundancy. DOI: 10.25791/pribor.2.2022.1320 Pp. 07-12.