Instruments and Systems: Monitoring, Control, and Diagnostics Annotation << Back Methodological Approach to Reducing and Evaluating Hardware and Time Redundancy of Means of Detecting and Correcting Packet Errors in Information Storage and Transmission Devices of Telecommunications Systems A.A. PAVLOV, A.N. TSARKOV, A.YU. ROMANENKO, A.A. MIKHEEV The necessity of developing a methodological apparatus related to the construction of a code that corrects errors in a given number of bytes of information with algebraic syndrome decoding and the estimation of hardware and time costs associated with this purpose is justified. The rules for constructing a correction code that corrects errors in a given number of bytes of information are presented, which implements a linear procedure for constructing a correction code with syndrome decoding and using an additive error vector, which allowed reducing hardware costs for constructing a decoding device (reducing the amount of memory for storing the values of error vectors). Expressions are obtained for estimating hardware costs for encoding and decoding information using the proposed packet error correction method. Comparison of hardware and time redundancy in implementation of proposed method of correction of packet errors with existing ones is performed. Proposed method of error correction in given number of bytes of information with additive generation of error vector has regular and relatively simple procedure of code construction, allows to reduce hardware and time costs for information encoding and decoding. Keywords: digital data transmission system, correcting algebraic linear code, error bytes, information bits, check bits, error syndrome, additive error vector. DOI: 10.25791/pribor.6.2021.1271 Pp. 63-70.