Instruments and Systems: Monitoring, Control, and Diagnostics Annotation << Back Methodical apparatus of functional code error correction information processing devices with minimal information and hardware redundancy A.A. PAVLOV, A.N. TSARKOV, D.A. KORSUNSKY, V.Z. VOLKOV, A.V. GUSEV The necessity of detecting and correcting errors of arithmetic logic units (ALU) of computer processors is grounded. Requirements for methods of detecting and correcting errors in ALU processors are defined, which include: the detecting ability of the control method, time and hardware costs. The analysis of existing methods for ensuring the fault tolerance of information processing devices has been carried out and their disadvantage has been revealed, which consists of a large hardware redundancy. A regular procedure is proposed for constructing a fault-tolerant arithmetic logic unit of a computer based on the formation of a redundant channel due to the functional redundancy of the processor and the use of an algebraic linear code to control storage devices and its adaptation to control arithmetic and logical operations. The regularities are revealed that allow the use of functional devices of the processor to perform basic and duplicate functions. The calculation of hardware costs for the formation of a redundant channel and a comparative evaluation of the probability of failure-free operation from the use of the proposed reservation method has been carried out. The use of the proposed backup method, in comparison with the majority method, allows increasing the probability of failure-free operation of the computer, reducing overall hardware costs by a third, and reducing the hardware costs for building an ALU processor by 2.5 times. Keywords: algebraic linear code, information bits, control bits, error syndrome, single and double errors, information redundancy, instrumental redundancy, arithmetic operations, logical operations. DOI: 10.25791/pribor.04.2019.582 Contacts: E-mail: Pavlov_iif@mail.ru Pp. 01-10.